//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
/******************************************************************************
**
**  COPYRIGHT (C) 2001, 2002 Intel Corporation.
**
**  This software as well as the software described in it is furnished under
**  license and may only be used or copied in accordance with the terms of the
**  license. The information in this file is furnished for informational use
**  only, is subject to change without notice, and should not be construed as
**  a commitment by Intel Corporation. Intel Corporation assumes no
**  responsibility or liability for any errors or inaccuracies that may appear
**  in this document or any software that may be provided in association with
**  this document.
**  Except as permitted by such license, no part of this document may be
**  reproduced, stored in a retrieval system, or transmitted in any form or by
**  any means without the express written consent of Intel Corporation.
**
**  FILENAME:       xllp_MMC.h
**
******************************************************************************/
// note that this will not be in there in the end; this is only for testing purposes
#ifndef __MMC_H__
#define __MMC_H__

#include "xllp_common.h"

/**
  MMC Register Definitions
**/

typedef struct
{
    XLLP_VUINT32_T MMC_STRPCL;     /* Control to start/stop mmc/sd clock */
    XLLP_VUINT32_T MMC_STAT;       /* status register*/
    XLLP_VUINT32_T MMC_CLKRT;      /* clock rate */
    XLLP_VUINT32_T MMC_SPI;        /* SPI mode control bits */
    XLLP_VUINT32_T MMC_CMDAT;      /* command/response/data sequence control */
    XLLP_VUINT32_T MMC_RESTO;      /* expected response timout */
    XLLP_VUINT32_T MMC_RDTO;       /* expected data read timeout */
    XLLP_VUINT32_T MMC_BLKLEN;     /* block length of data transaction */
    XLLP_VUINT32_T MMC_NUMBLK;     /* number of block for block mode */
    XLLP_VUINT32_T MMC_PRTBUF;     /* partial mmc_txfifo written  */
    XLLP_VUINT32_T MMC_I_MASK;     /* interrupt mask */
    XLLP_VUINT32_T MMC_I_REG;      /* interrupt register */
    XLLP_VUINT32_T MMC_CMD;        /* index of current command */
    XLLP_VUINT32_T MMC_ARGH;       /* MSW part of the current command arg */
    XLLP_VUINT32_T MMC_ARGL;       /* LSW p art of the current command arg */
    XLLP_VUINT32_T MMC_RES;        /* response fifo */
    XLLP_VUINT32_T MB_RXFIFO;      /* receive fifo for single byte */
    XLLP_VUINT32_T MB_TXFIFO;      /* transmit fifo for single byte */
    XLLP_VUINT32_T MMC_RDWAIT;     /* reserved for different fifo */
    XLLP_VUINT32_T MMC_BLKS_REM;   /* SD CMDAT register */

} XLLP_MMC_T, *P_XLLP_MMC_T;

/*  mmc start and stop clock register  */
#define XLLP_STRPCL_STPCLK   XLLP_BIT_0;   // stop clock; writing 1 stops the MMC clock
#define XLLP_STRPCL_STRTCLK  XLLP_BIT_1;   // start clock; writing 1 starts the MMC clock
                                           // bit automatically cleared to 0

// MMC  status register
#define  XLLP_STAT_TORD           XLLP_BIT_0   // read timed out
#define  XLLP_STAT_TORSPNS        XLLP_BIT_1   // card response timed out
#define  XLLP_STAT_CRCWRERR       XLLP_BIT_2   // card observed erroneous transmission of data
#define  XLLP_STAT_CRCRDERR       XLLP_BIT_3   // crc error on recieved data
#define  XLLP_STAT_DATAERRTKN     XLLP_BIT_4   // spi data error token has been received
#define  XLLP_STAT_RESCRCERR      XLLP_BIT_5   // response crc error
#define  XLLP_STAT_CLKEN          XLLP_BIT_8   // MMC clock is on
#define  XLLP_STAT_FLASHERR       XLLP_BIT_9   // MMC clock is on
#define  XLLP_STAT_SPIWRERR       XLLP_BIT_10  // data rejected by card due to error
#define  XLLP_STAT_DATATRANDONE   XLLP_BIT_11  // data transmission card has completed
#define  XLLP_STAT_PRGDONE        XLLP_BIT_12  // card has finished programming and is not busy
#define  XLLP_STAT_ENDCMDRES      XLLP_BIT_13  // command and response sequence has completed
#define  XLLP_STAT_RDSTALLED      XLLP_BIT_14  // read transfer stalled due to response RD_WAIT
#define  XLLP_STAT_SDIOINT        XLLP_BIT_15  // an SDIO interrupt occured
#define  XLLP_STAT_SDIOSUSPENDACK XLLP_BIT_16  // SDIO data transfer suspended by SDIO card

//  MMC Clock rate register
#define  XLLP_CLKRT    0x7

typedef enum
{
    XLLP_MMC_19_5MHz  = 0x0,
    XLLP_MMC_9_75MHz  = 0x1,
    XLLP_MMC_4_88MHz  = 0x2,
    XLLP_MMC_2_44MHz  = 0x3,
    XLLP_MMC_1_22MHz  = 0x4,
    XLLP_MMC_609KHz   = 0x5,
    XLLP_MMC_304KHz   = 0x6

}XLLP_MMC_CLKRATE;

//  MMC SPI register
#define  XLLP_MMC_SPI_MODE       XLLP_BIT_0   //  enables spi mode
#define  XLLP_MMC_SPI_CRCEN      XLLP_BIT_1   //  enable crc generation and verification
#define  XLLP_MMC_SPI_CSEN       XLLP_BIT_2   // enables spi chip select
#define  XLLP_MMC_SPI_CSADDR     XLLP_BIT_3   // 1 enables CS1  0 enable CS0

//  MMC command data register
#define  XLLP_MMC_CMDAT_RESTYPE 0x3
typedef enum
{
    XLLP_MMC_NORESPONSE  = 0x0,
    XLLP_MMC_MMCSPIR1    = 0x1,
    XLLP_MMC_MMCSPIR2    = 0x2,
    XLLP_MMC_MMCR3       = 0x3

}XLLP_MMC_RESPFRMT;

#define  XLLP_MMC_CMDAT_DATAEN      XLLP_BIT_2   //  current command includes data
#define  XLLP_MMC_CMDAT_WRRD        XLLP_BIT_3   // 0 specifies a read  1 specifies a write
#define  XLLP_MMC_CMDAT_STRMBLK     XLLP_BIT_4   //current command is in stream block mode
#define  XLLP_MMC_CMDAT_BUSY        XLLP_BIT_5   // specifies whether a busy signal is expected after
                                                 //  after current command   for no data trans. only
#define  XLLP_MMC_CMDAT_INIT        XLLP_BIT_6   // precede command sequence with 80 clocks
#define  XLLP_MMC_CMDAT_DMAEN       XLLP_BIT_7   //  DMA mode
//this is also part of the CMDAT reg but specificly only if MMC_SD_CMDAT register is used
#define  XLLP_MMC_CMDAT_SD4DAT      XLLP_BIT_8   // (1)enable 4 bit data transfer; only valid for SD

#define  XLLP_MMC_CMDAT_STOPTRANS   XLLP_BIT_10  // stops data transfers
#define  XLLP_MMC_CMDAT_SDIOINTEN   XLLP_BIT_11  // enables control to look for SDIO interrupts from card
#define  XLLP_MMC_CMDAT_SDIOSUSPEND XLLP_BIT_12  // SDIO CMD52, suspend current data transfers
#define  XLLP_MMC_CMDAT_SDIORESUME  XLLP_BIT_13  // SDIO CMD52, resumes a currently suspended data transfer

//  MMC Resto register
#define  XLLP_MMC_RESTOBITS    0x7f

//  MMC read time out register
#define  XLLP_MMC_RDTOBITS     0xffff

//  MMC block length register
#define  XLLP_MMC_BLKLENBITS   0xfff

//  MMC number of blocks register
#define  XLLP_MMC_NUMBLKBITS   0xffff

//  MMC partial full buffer register
#define  XLLP_MMC_PRTBUF       XLLP_BIT_0   //  buffer is partially full and must be swapped to the other transmit buffer

//  MMC interrupt mask register
#define  XLLP_MMC_I_MASK_DATATRANSDONE    XLLP_BIT_0   // data transfer is done
#define  XLLP_MMC_I_MASK_PRGDONE          XLLP_BIT_1   // programming is done
#define  XLLP_MMC_I_MASK_ENDCMDRES        XLLP_BIT_2   //  end command response
#define  XLLP_MMC_I_MASK_STOPCMD          XLLP_BIT_3   // ready for stop transaction command
#define  XLLP_MMC_I_MASK_CLKISOFF         XLLP_BIT_4   // clock is off
#define  XLLP_MMC_I_MASK_RXFIFORDREQ      XLLP_BIT_5   //receive fifo read request
#define  XLLP_MMC_I_MASK_TXFIFOWRREQ      XLLP_BIT_6   //  transmit fifo write request
#define  XLLP_MMC_I_MASK_TINT             XLLP_BIT_7   //  transmit fifo write request
#define  XLLP_MMC_I_MASK_DATERR           XLLP_BIT_8   // data error
#define  XLLP_MMC_I_MASK_RESERR           XLLP_BIT_9   // response error
#define  XLLP_MMC_I_MASK_RDSTALLED        XLLP_BIT_10  //card stalled in response to RD_WAIT
#define  XLLP_MMC_I_MASK_SDIOINT          XLLP_BIT_11  //  SDIO Interrupt
#define  XLLP_MMC_I_MASK_SDIOSUSPENDACK   XLLP_BIT_12  //  SDIO data trans. suspended by SDIO card

//  MMC current interrupt register
#define  XLLP_MMC_I_REG_DATATRANSDONE     XLLP_BIT_0   // data transfer is done   cleared by the mmc_stat[dataDone]
#define  XLLP_MMC_I_REG_PRGDONE           XLLP_BIT_1   // programming is done   cleared by the mmc_stat[prgDone]
#define  XLLP_MMC_I_REG_ENDCMDRES         XLLP_BIT_2   //  end command response   cleared by the mmc_stat[endCmdRes]
#define  XLLP_MMC_I_REG_STOPCMD           XLLP_BIT_3   // ready for stop transaction command   cleared when cmd12 is loaded
#define  XLLP_MMC_I_REG_CLKISOFF          XLLP_BIT_4   // clock is off   cleared by the mmc_stat[clkEn]
#define  XLLP_MMC_I_REG_RXFIFORDREQ       XLLP_BIT_5   //receive fifo read request  cleared after each read but immediately
                                                       // set again unless the fifo is empty
#define  XLLP_MMC_I_REG_TXFIFOWRREQ       XLLP_BIT_6   //  transmit fifo write request  cleared after each write but immediately
                                                       // set again unless the fifo is empty
#define  XLLP_MMC_I_REG_TINT              XLLP_BIT_7   //  transmit fifo write request
#define  XLLP_MMC_I_MASK_DATERR           XLLP_BIT_8   // data error has occured
#define  XLLP_MMC_I_MASK_RESERR           XLLP_BIT_9   // response error has occured
#define  XLLP_MMC_I_MASK_RDSTALLED        XLLP_BIT_10  //card stalled in response to RD_WAIT
#define  XLLP_MMC_I_MASK_SDIOINT          XLLP_BIT_11  //  SDIO Interrupt has occured
#define  XLLP_MMC_I_MASK_SDIOSUSPENDACK   XLLP_BIT_12  //  SDIO data trans. suspended by SDIO card

//  MMC Command registers that specifies the commands
#define  XLLP_MMC_CMDBITS     0x3f

typedef enum
{
    XLLP_MMC_SPICMD0  = 0x0, // go idle state
    XLLP_MMC_SPICMD1  = 0x1, // send op command
    XLLP_MMC_CMD2     = 0x2, // all send cid
    XLLP_MMC_CMD3     = 0x3, // set relative addr
    XLLP_MMC_CMD4     = 0x4, // set dsr
    XLLP_MMC_CMD7     = 0x7, // select/deselect card
    XLLP_MMC_SPICMD9  = 0x9, // send csd
    XLLP_MMC_SPICMD10 = 0xa, // send cid
    XLLP_MMC_CMD11    = 0xb, //  read data until stop
    XLLP_MMC_CMD12    = 0xc, // stop transmission
    XLLP_MMC_SPICMD13 = 0xd, // send status
    XLLP_MMC_CMD15    = 0xf, // go inactive state
    XLLP_MMC_SPICMD16 = 0x10,//  set block length
    XLLP_MMC_SPICMD17 = 0x11,// read single block
    XLLP_MMC_CMD18    = 0x12,//  read multiple block
    XLLP_MMC_CMD20    = 0x14,// write data until stop
    XLLP_MMC_SPICMD24 = 0x18,// write block
    XLLP_MMC_CMD25    = 0x19,// write multiple block
    XLLP_MMC_CMD26    = 0x1a, // program CID
    XLLP_MMC_SPICMD27 = 0x1b, // program CSD
    XLLP_MMC_SPICMD28 = 0x1c, // set write prot
    XLLP_MMC_SPICMD29 = 0x1d,  // clr write prot
    XLLP_MMC_SPICMD30 = 0x1e, // send write prot
    XLLP_MMC_SPICMD32 = 0x20,  // tag sector start
    XLLP_MMC_SPICMD33 = 0x21, // tag sector end
    XLLP_MMC_SPICMD34 = 0x22, // untag sector
    XLLP_MMC_SPICMD35 = 0x23, // tag erase group start
    XLLP_MMC_SPICMD36 = 0x24, //  tag erase group end
    XLLP_MMC_SPICMD37 = 0x25,  // untag erase group
    XLLP_MMC_SPICMD38 = 0x26,  // erase
    XLLP_MMC_CMD39    = 0x27, //fast IO
    XLLP_MMC_CMD40    = 0x28, // go irq state
    XLLP_MMC_SPICMD42  = 0x2a, // lock-unlock
    XLLP_MMC_SPICMD55  = 0x37, // app cmd
    XLLP_MMC_SPICMD56  = 0x38, //  gen cmd
    XLLP_SPI_CMD58  = 0x3a,  // read ocr
    XLLP_SPI_CMD59  = 0x3b,  // crc on-off
    XLLP_MMC_CMD60  = 0x3c, // reserved for manufacturer
    XLLP_MMC_CMD61  = 0x3d,  // reserved for manufacturer
    XLLP_MMC_CMD62  = 0x3e, // reserved for manufacturer
    XLLP_MMC_CMD63  = 0x3f,  // reserved for manufacturer
    XLLP_SD_ACMD6   = 0x06,//0x146,
    XLLP_SD_ACMD13  = 0x0d,//0x14D,
    XLLP_SD_ACMD22  = 0x16,//0x156,
    XLLP_SD_ACMD23  = 0x17,//0x157,
    XLLP_SD_ACMD41  = 0x29,//0x169,
    XLLP_SD_ACMD42  = 0x2a,//0x16a,
    XLLP_SD_ACMD51  = 0x33,//0x173

} XLLP_MMC_CMD;

//  MMC upper 16 bits of the argument for the current command
#define  XLLP_MMC_ARGHBITS     0xffff

//  MMC lower 16 bits of the argument for the current command
#define  XLLP_MMC_ARGLBITS     0xffff

//  MMC response fifo
#define  XLLP_MMC_RESFIFOBITS  0xffff

//  MMC  Receive fifo
#define  XLLP_MMC_RXFIFOBYTE   0xff

//  MMC transmit fifo
#define  XLLP_MMC_TXFIFOBYTE   0xff

// SDIO RD_WAIT register
#define  XLLP_SDIO_RDWAITEN     XLLP_BIT_0  // RD_WAIT enabled
#define  XLLP_SDIO_RDWAITSTART  XLLP_BIT_1  // restart the read data transfer

//  mmc blks remaining register
#define  XLLP_MMC_BLKSREM       0xffff      // the number of blocks not transferred

#ifdef __cplusplus
#define Extern_C extern "C"
#else
#define Extern_C extern
#endif //__cplusplus
// function prototypes
Extern_C  void XllpMmcSdHWInit( P_XLLP_GPIO_T GpioReg,
                P_XLLP_CLKMGR_T ClckReg,
                P_XLLP_BCR_T BcrReg );

Extern_C  void XllpMmcSdHwShutdown( P_XLLP_CLKMGR_T ClckReg,
                P_XLLP_BCR_T BcrReg );

Extern_C  XLLP_BOOL_T XllpMmcSetUpClock( P_XLLP_MMC_T mmcRegs,
                XLLP_MMC_CLKRATE rate,
                XLLP_BOOL_T strClck );

Extern_C  XLLP_UINT32_T XllpMmcXtractResp( P_XLLP_MMC_T mmcRegs,
                P_XLLP_UINT16_T buff,
                XLLP_UINT32_T TineOut);

Extern_C  XLLP_BOOL_T XllpMmcStartClock( P_XLLP_MMC_T SDMMCRegs );

Extern_C  XLLP_BOOL_T XllpMmcStopClock( P_XLLP_MMC_T SDMMCRegs );

Extern_C XLLP_BOOL_T XllpMmcSdPrepareAndSetup( P_XLLP_MMC_T SDMMCRegs,
                XLLP_MMC_CMD Cmd,
                XLLP_INT32_T Arg,
                XLLP_INT16_T noBlocks,
                XLLP_INT16_T Resp,
                XLLP_BOOL_T xMode );

Extern_C  XLLP_BOOL_T XllpMmcSdSetupCmd( P_XLLP_MMC_T mmcRegs,
                XLLP_MMC_CMD cmd,
                XLLP_INT32_T arg,
                XLLP_INT32_T To,
                XLLP_BOOL_T fourBitMode );

Extern_C  XLLP_BOOL_T XllpMmcSdSetupXCmd( P_XLLP_MMC_T mmcRegs,
                XLLP_INT32_T FlSz,
                XLLP_INT32_T BlkSz );

Extern_C  void XllpMmcSdInts( P_XLLP_MMC_T mmcRegs,
                XLLP_INT8_T SetMask );

Extern_C XLLP_BOOL_T XllpMmcSdStatus( P_XLLP_MMC_T SDMMCRegs,
                XLLP_INT32_T Status,
                XLLP_INT32_T TimeOut,
                XLLP_BOOL_T BitOne );

#endif // end of .h fi
